NEWS

Fan-out wafer level packaging set to expand

Wednesday, Jul 15, 2015

The expansion of fan-out is finally coming, says Rich Rogoff, Vice President and General Manager, Lithography Systems Group at Rudolph Technologies.

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.

It was originally introduced by Infineon in the fall of 2007. Called eWLB, or embedded wafer-level ball grid array technology, it enables all operations to be performed highly parallel at wafer level. In August of 2008, STMicroelectronics, STATS ChipPAC, and Infineon signed an agreement to jointly develop the next-generation eWLB, based on Infineon’s first-generation technology.

Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

STATS ChipPAC’s eWLB high volume manufacturing process, for example, today includes automated wafer reconstitution (including wafer-level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 200mm and 300mm diameters can be supported.

According to a recent report from Yole Développement, the fan-out WLP (FOWLP) market will reach almost $200M in 2015, with 30% CAGR in the coming years. Yole analysts say FOWLP started volume commercialization in 2009/2010 and started promisingly, with an initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. In 2012 big fabless wireless/mobile players started slowly volume production after qualifying the technology.

It faced strong competition from other packaging technologies, such as wafer-level chip scale packaging (WLCSP) in 2013/2014. Intel Mobile also backed off from the technology, and the main manufacturers reduced their prices in 2014, creating a transition phase with low market growth.

Strong growth is now expected, hoped in part by the arrival of 2nd generation FOWLP. “Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size”, explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement.

Rudolph’s Rogoff believes it will be implemented in a wafer form for the next year or two, but will ultimately transition to a panel-based approach. “The big question for the industry is are they going to move to panels?” Rogoff asked. “From a lithography perspective, the tools are ready today. As the demand goes up, there will be a push also for a switch,” he said. “Development of panels has already started and will continue to increase in activity over the next year.”

In an article in Solid State Technology published in 2014, titled “A square peg in a round hole: The economics of panel-based lithography for advanced packaging,” Rogoff said moving from round wafers to rectangular panels (“panel-ization”) saves corner space, delivering a roughly 10% improvement in surface utilization. The larger size of the substrate and the improved fit between the mask and substrate reduce the transfer overhead by a factor of 5. The potential reduction in throughput resulting from an increase in the number of alignment points is more than offset by the improvements in throughput. Compared to a 1X stepper on wafers, panel-based processes can reduce lithography cost per die by as much as 40%.

One of the advantage of Rudolph Technologies’ JetStep Panel System (JetStep S3500) is that it can handle such rectangular panels. Both the panel and wafer 2X reduction steppers offer many advantages — based in part on Azores’ 6700 platform which was developed for LCDs — including the largest printable field-of-view, programmable aperture blades and large on-tool reticle library, large depth-of-focus along with autofocus to accommodate 3D structures in advanced packaging, very large working distance, and warped substrate handling (+/- 6mm). The wafer system (JetStep W2300) features programmable wafer edge protection, enabling a variable edge exclusion zone of 0.5-5 mm. The systems also feature a large (17mm) working distance between the lens and the substrate, which helps avoid a common maintenance issue on 1X systems.

Rogoff said the ability to handle warped wafers is increasingly important. “We’ll always be putting the best focus point in the middle of our depth of focus range. If there’s any variation due to substrate warp, we can go up a little and down a little and we’re still going to be in focus,” he said.

The large working distance helps eliminate problems with thick resists, which can outgas and potentially contaminate the lens. “We’re so far away — and we also have some purging in the area – we don’t have that issue. The less you have to take the machine down to clean it, the better,” he said.

When it comes to fan-out, the challenge is being able to manage the overlay performance over a large field area. “Our competitors like to say it can’t be done, yet we prove it can,” Rogoff said. “The larger the field is, the more die you get in it, so the more variations you’re likely to see. With our ability to correct for intrafield parameters, we can extract out that variation so what’s left is just random noise.”

If the random noise gets too high, another solution Rudolph can provide is a combination of stepper modeling capability with inspection. “You can measure the die placement on a high speed inspection tool, throw that data into the modeling software and spit out the stepping model for the stepper,” Rogoff explained. “This is something we’re continuing to develop. The first round is available and as the fan-out technology gets more complex, we’re continuing to expand on that.”

 

electroiq.com

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